abstract Every notion of a component for the development of embedded systems has to take heterogeneity into account: components may be hardware or software or OS, synchronous or asynchronous, deterministic or not, detailed w.r.t. time or not, detailed w.r.t. data or not, etc. A lot of approaches, following Ptolemy, propose to define several Models of Computation and Communication (MoCCs) to deal with heterogeneity, and a framework in which they can be combined hierarchically. This paper presents the very first design of a component model for embedded systems called 42. We aim at expressing fine-grain timing aspects and several types of concurrency as MoCCs, but we require that all the MoCCs be programmed in terms of more basic primitives. 42 is meant to be an abstract description level, intended to be translated into an existing language (e.g., Lustre) for execution and property validation purposes.
abstractTransaction-Level Modeling (TLM) for systems-on-a-chip (SoCs) has become a standard in the industry, using SystemC. With SystemC-TLM, it is possible to develop an executable virtual prototype of a hardware platform, so that software developers can start writing code long before the actual chip is available. A hardware model in SystemC-TLM is very abstract, compared to the detailed RTL model. It is clearly component-based, with guidelines defining how components should be designed for use in any TLM context. However, these guidelines are quite informal for the moment. In this paper, we establish a structural correspondence between SystemC-TLM and a formal component-model for embedded systems called 42, for which we have defined a notion of control contract, and an execution mode for systems made of components contracts. This is a way of formalizing SystemC-TLM principles. Moreover, it allows the combined use of SystemC-TLM components with 42 components. Demonstrating that such a combined use is possible is key to the adoption of formal components definitions in the community of TLM users.